Serving Eastern Massachusetts
|Course Name:||SystemVerilog 102 (SV102): Verification Constructs|
|Time & Date:||You decide, see Class Description below|
|Location:||Your PC, See Class Description below|
|Speakers:||Online self-paced class|
SytemVerilog is an extensive set of language constructs to the IEEE 1364-2001 standard. It’s meant to aid in the creation and verification of models. There are two parts to the language extension. The first part covered by SV101, is new design constructs. SV102, this class, covers verification constructs. SystemVerilog102, like all CBE classes, is lab based.
There are over 30 verification labs/examples giving comprehensive “how to” examples of most SystemVerilog verification language constructs. There are working solutions for each lab and the students can use the lab database for developing their own assertions later. The class is also self paced. All the work can be done independently by the engineers, at their own computer, and at their own pace.
There are self-grading quizzes for each chapter that allow the student to see if he/she is learning the material.
The goals of this course are to make you familiar with the new part of the language.
Students taking SystremVerilog102 will have a 90-day access to it. The lab database you will be able to download and is yours to keep.
Hardware engineers. SystemVerilog is the next stage in the evolution of Verilog. Every Verilog engineer will need to know this information.
Students must have a computer with Internet access. The class is written in HTML so any browser with a Flash (version 6 or higher) player will work.
To do the lab students must have access to an SystemVerilog simulator.
SV102 - An Introduction
SystemVerilog - Verification Flow Overview
lab1-- Immediate Assertions
lab2-- Concurrent Assertions
Referencing a Sequence
lab4-- A Sequence Referencing A Sequence
Using Formal Arguments in a Sequence
lab5-- Using Formal Argument With A Sequence
Concatenation of Sequences
Specifying a Range of Clock Ticks
lab7-- Clock Range
Unconditionally Extending a Sequence
lab8-- Unconditionally Extending A Sequence
lab9-- Consecutive Repeats
lab10-- Infinite Repeats
lab11-- Goto Repeat Operator
Value Change Functions
First match in a sequence
Using Formal Arguments
lab22-- Using Formal Arguments With A Property
lab23-- Overlapping Implications
lab24-- Non-Overlapping Implications
Inverting a property
lab25-- Inverting A Property
lab27-- disable iff
lab28-- Action Blocks
Binding an SVA module Parameter passing in a bind directive
Jay Tyer, a graduate of WPI, has been teaching Verilog, Timing Analysis and various EDA tools for 17 years. He has been working in the development of online classes for several years.
Ongoing - there are no "before" or "after" dates.
IEEE Members $300