Course Description

Course Name:	Practical Phase-Locked-Loop Design
Time & Date:	Day 1: PLL Fundamentals - 8:30 AM - 4:30 PM, Tuesday November 16 (PLL Fundamentals) Day 2: Jitter and Phase Noise in PLLs - 8:30 AM - 4:30 PM, Wednesday November 17 (Jitter and Phase Noise in PLLs)
Location:	Holiday Inn Select Hotel, 15 Middlesex Canal Park Rd, Woburn, MA
Speaker:	John McNeill, Worcester Polytechnic Institute
Text:	Designer’s Guide to Jitter in Ring Oscillators, by J. McNeill and D. Ricketts, list price $129

Course Summary:

This two-day course covers practical issues involved in design of phase-locked loop (PLL) systems for applications such as frequency synthesis, serial data communication, clock and data recovery. The intent is to provide intuitive insight to design decisions at both the system and component levels.

The first day of the course covers the fundamentals of PLL operation, including system level concepts and design decisions, loop components, performance metrics, and measurement issues. The second day of the course covers jitter and phase noise, which set limits to PLL performance in many applications. Simple techniques are presented for relating system-level jitter and phase noise performance to component-level design decisions.

Throughout both days, the emphasis will be on practical design examples, relating predictions from design procedures to measured performance. Representatives from manufacturers Agilent, LeCroy, and Tektronix will be present with demonstrations of jitter and phase noise measurement equipment and techniques.

Who should attend

Engineers working in system-level, board-level, and/or component-level design in PLL application areas
Test engineers concerned with time domain or frequency domain measurement issues
IC design engineers working with PLL systems or component subsystems such as voltage-controlled oscillators (VCOs)
Application and product engineers working to interface with and satisfy customer requirements for PLL performance
Engineers seeking greater understanding of issues involved in PLL applications such as frequency stability, timing jitter and accuracy, etc.

Benefits of attending

Better understanding of fundamental concepts
Examples of real-world design techniques for hitting performance targets with less design time
See demonstration of state-of-the-art measurement techniques

OUTLINE:

Day 1: Phase-Locked Loop (PLL) Fundamentals

Applications:

Frequency Synthesis

Communications

SERDES

Clock-Data Recovery

others ...

PLL System concepts

Phase, Frequency

PLL as a Control System

Loop Components

Voltage Controlled Oscillator

Phase / Frequency Detection

Loop Filter

Digital PLL

System Level Design Issues

Analog vs. Digital

Controls: Loop Bandwidth, small signal behavior

Large signal: Acquisition

Performance Measurement Techniques

Specifications

Time Domain vs. Frequency Domain

Instrumentation

Measurement Techniques

Example Design

Day 2: Jitter and Phase Noise in PLLs

Review

PLL System Concepts

Jitter (Time Domain) vs. Phase Noise (Frequency Domain) Voltage controlled Oscillators

Ring

Multivibrator

Characterizing Jitter

Measurement Techniques

State-of-the-Art Instrumentation

Relating Time, Frequency domains

Sources of Jitter

Random: Thermal Noise, Shot Noise

Deterministic: Power Supply noise, interference, coupling

Designing for Low jitter

System Level

discrete vs. integrated

(integrated) Circuit Level

CMOS vs. bipolar

Example Designs

Speaker bio:

John McNeill has over 20 years of experience in design of low noise, high precision, analog and mixed signal circuits and systems. Since 1994 he has been with the Electrical and Computer Engineering department of Worcester Polytechnic Institute, where in 1999 he received WPI’s campus-wide award for Outstanding Teaching, and in 2007 was one of the first recipients of WPI’s Exemplary Faculty award recognizing accomplishment in teaching, research, and service. In 2006, McNeill and co-authors Coln and Larivee received the Lewis Winner Award for Outstanding Paper at the 2005 IEEE International Solid-State Circuits Conference.

Text, course notes and coffee breaks are included with the course registration.

Decision (Run/Cancel) Date for this Courses is Monday, November 9, 2010

FEES

One-Day

Payment received by November 4: IEEE Members $280

Payment received by November 4: Non-members $310

Payment received after November 4: IEEE Members $310

Payment received after November 4: Non-members $340

Two-Days

Payment received by November 4: IEEE Members $425

Payment received by November 4: Non-members $450

Payment received after November 4: IEEE Members $450

Payment received after November 4: Non-members $475