Course Description:

This course introduces the Serial RapidIO specifications for use in real-time embedded applications. The first part of the course focuses on gaining an understanding of the current Rev 1.3 specifications for Serial RapidIO highlighting areas of concern for real-time embedded application development. The latter part covers the new Rev 2.0 specifications including Data Streaming, Virtual Channels, Flow Control and Traffic Management.

Overview:

A 2 day lecture-only course introducing the Serial RapidIO hardware specifications. The course focuses on the design and development of embedded systems using Serial RapidIO hardware.

Course Objectives:

• To provide an understanding of the essentials of Serial RapidIO hardware design.

• To give you practical understanding of the Serial RapidIO standard hardware specifications.

• To give you the confidence to apply these new concepts to your next Serial RapidIO hardware design.

• To gain an understanding of the new Rev 2.0 Specifications

Students will learn:

• The terminology and use of Serial RapidIO hardware.

• Internals of the Serial RapidIO specifications

• The types of embedded systems that can use Serial RapidIO

• When to use Serial RapidIO and when to use Ethernet

• When to use Serial RapidIO and when to use PCI-X

Pre-requisites:   General knowledge of packet-based architectures such as TCP/IP.

Who Should Attend: The course is designed for real-time engineers who are embarking on a project using Serial RapidIO for the first time. It is also targeted at experienced designers requiring a refresher course. This course will clearly demonstrate both the strengths and weaknesses of the Serial RapidIO hardware specifications.

Course Materials: Student Handbook

Course Workshop: The course makes use of existing Serial RapidIO hardware and software products. For on-site courses it may be possible for us to utilize specific hardware on request, or offer the course without any hardware.

Course Outline:

The Transition to Packet Switching:

• PCI Bus History

• Interconnect Trends

• Moving to Switch Fabrics

• PCI Express Overview

• The PCI Express Packet

• Increasing Switch Fabric Performance

• RapidIO History

An Overview of Serial RapidIO:

• System View

• Rev 1.3 Specifications

• The Layer Model

• Packet Building

• The Purpose of Control Symbols

• Request/Response Sequence

• Technical Features

The Logical Layer:

• The 3 Basic Logic Traffics

• Packet Alignment Rules

• Deadlock Avoidance

• The Input/Output Logic Traffic

• The Message Logic Traffic

• The Global Shared Memory Logic Traffic

• The Data Streaming Logical Specification

• The Flow Control Logical Layer

The Transport Layer:

• Packet Routing via Target ID

• Routing Table Format

• Multicast Extensions (Rev 1.3)

• Hardware Duplication of Posted Write Packets

• Capability Registers (CARs)

• Control and Status Registers (CSRs)

System Bringup:

• System Exploration and Initialization

• System Enumeration

• Standard Bringup Function

The Physical Layer:

• Alignment Rules

• Packet Acknowledgement

• Multicast Events

Error Management:

• Packet Priority and Flow Control:

• The LP-LVDS 8/16 Interface:

• The LP-S 1x/4x Interface (1G, 2.5G, 3.125G):

• The New Rev 2.0 Specification:

  - Rev 2.0 Specifications

  - The LP-S 1x/2x/4x/8x Interface (5.0G, 6.25G)

  - General Overview

  - New Features

Benefits of the Rev 2.0 Specification:

• Backwards Compatibility

• New Physical Layers

• New PHYs

• Extended Control Symbol and New Idle

Data Plane Overview (Rev 2.0):

• New Data Streaming Packet Format

• The Addition of Virtual Channels (VCs)

• The Endpoint Flow Control Arbitration Specification

• The New Traffic Management Specification

• The Virtual Output Queue Specification

Data Streaming Support:

• Type 9 Packet Format

• 64K PDU Sizes

• Data Streams Between Endpoints

• Multicast Support

• Lossy Transaction Support

• Class of Service (COS) Support

• Arbitrary Protocol Encapsulation

Virtual Channels:

• Independently Managed Subchannels

• No Guaranteed Ordering Between VCs

• Individual Link Layer Flow Control

Continuous Traffic vs Reliable Traffic:

• Reliable Traffic

• Reserving of Bandwidth

• Scheduling

• Overall Utilization of the Switch Fabric

Flow Control Arbitration:

• Extending Existing Type 7 Congestion Management

• Endpoint Management

• Preventing Traffic Admittance

• Extended Control Symbol and New Idle

Traffic Management & Virtual Output Queuing:

• Traffic Flow Coordination

• Extended Header Type 9 Packet Format

• Throttling Traffic

• On/Off, Rate-based and Credit-based Schemes

Performance Summary Impact:

• Physical Layer Status Messages

• Reducing Head-of-Line (HOL) Blocking

• New Extended Control Symbol Usage

Lecturer: Mike McCullough is Director of Professional Services for Embedded Planet. Mike has a BS in Computer Engineering and an MS in Systems Engineering from Boston University. A 20-year electronics veteran, he has held various positions at Wind River Systems, Lockheed Sanders, Stratus Computer and Apollo Computer. Embedded Planet is a provider of embedded systems hardware, Eclipse-based software development tools, training and consulting services for the embedded systems market.

New Dates are shown in RED

Decision/Cancel Date for this course is Thursday, April 3, 2008

Course Fee Schedule:

On-line Registration and Payment

This course has been cancelled.  If you have any questions or concerns, please contact the IEEE office at 781-245-5405.

Copyright © 2008 IEEE Boston Section. All rights reserved.
Maintained by R M Stelting

Updated Thursday April 03, 2008